With the increasing down-scaling of integrated circuits and the increasingly demanding requirements to the speed of integrated circuits, transistors need to have higher drive currents with smaller dimensions. Fin Field-Effect Transistors (FinFET) were thus developed. FinFETs have increased channel widths. The increase in the channel width is achieved by forming channels that include portions on the sidewalls of the fins and portions on the top surfaces of the fins.
With the increasing down-scaling of integrated circuits, fins also become increasingly thinner, and the aspect ratios of the gaps between the fins become increasingly greater. The formation processes of the fins thus are more prone to the process variations in the respective manufacturing processes. In conventional FinFET manufacturing processes, the hard masks for forming the fins are defined first. The hard masks are then used as etching masks to etch the underlying semiconductor substrates, and the patterns of the hard masks are transferred to the underlying semiconductor substrates to from fins. In the etching of the semiconductor substrates, since the hard masks have pattern-dense regions and pattern-sparse regions, the pattern loading effect causes the fins in the pattern-dense regions and the pattern-sparse regions to be different from each other. The respective FinFETs are thus adversely affected.